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ISO/IEC 18372:2004

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Information technology - RapidIO(TM) interconnect specification

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The RapidIO architecture was developed to address the need for a high-performance low pin count packet-switched system level interconnect to be used in a variety of applications as an open standard. The architecture is targeted toward networking, telecom, and high performance embedded applications. It is intended primarily as an intra-system interface, allowing chip-to-chip and board-toboard communications at Gigabyte per second performance levels. It provides a rich variety of features including high data bandwidth, low-latency capability and support for high-performance I/O devices, as well as providing globally shared memory, message passing, and software managed programming models.


SDO ISO: International Organization for Standardization
Document Number ISO/IEC 18372
Publication Date Not Available
Language en - English
Page Count
Revision Level
Supercedes
Committee ISO/IEC/JTC 1/SC 25
Publish Date Document Id Type View
Not Available ISO/IEC 18372:2004 Revision