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IPC-T-50N

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Terms and Definitions for Interconnecting and Packaging Electronic Circuits

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Terms and Definitions for Interconnecting and Packaging Electronic Circuits
IPC-T-50N document is designed to provide definitions for terms commonly used in the electronics industry. The definitions are intended to provide sufficient clarity of detail such that a reader utilizing English as a second language could understand the subtleties of the meaning. IPC-T-50N contains over 550 new or revised terms, including new terminology for via structures, surface mount device types, solder bumps, solder alloys, soldering, dewetting, board fabrication processes and testing

SDO IPC: Institute for Interconnecting and Packaging Electronic Circuits
Document Number T50
Publication Date Not Available
Language en - English
Page Count
Revision Level N
Supercedes
Committee
Publish Date Document Id Type View
Not Available IPC-T-50N Revision
Not Available IPC-T-50M Revision
Not Available IPC-T-50K Revision
Not Available IPC-T-50J Revision
Not Available IPC-T-50H Revision
Not Available IPC-T-50G Revision
Not Available IPC-T-50N Revision
Not Available IPC-T-50M Revision
Not Available IPC-T-50M Revision
Not Available IPC-T-50K Revision
Not Available IPC-T-50H Revision