Logo

IPC/EIA-J-STD-028

Current Revision

Performance Standard for Construction of Flip Chip and Chip Scale Bumps

$143.00


Sub Total (1 Item(s))

$ 0.00

Estimated Shipping

$ 0.00

Total (Pre-Tax)

$ 0.00


Stay effortlessly up-to-date with the latest standard revisions. When new versions are released, they're automatically charged and delivered to you, ensuring seamless compliance.

Document Preview Not Available...

Performance Standard for Construction of Flip Chip and Chip Scale Bumps
This standard establishes construction detail requirements for bumps and other terminal structures used for Flip Chip Scale carriers. The specific standards for different terminations are appropriately matched to a particular interconnection process and include such diverse terminations as solder bumps, columns, non-melting stand-offs and conductive polymer deposits. The document articulates a set of designations and expectations for product performance for the manufacturer and the user of flip chip or chip scale devices. Recommendations are provided to implement the best commercial practices and evolving process improvements. Developed by IPC and EIA. 36 Pages. Released August 1999.

SDO IPC: Institute for Interconnecting and Packaging Electronic Circuits
Document Number J028
Publication Date Not Available
Language en - English
Page Count
Revision Level 0
Supercedes
Committee
Publish Date Document Id Type View
Not Available IPC/EIA-J-STD-028 Revision