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IPC/EIA-J-STD-026

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Semiconductor Design Standard for Flip Chip Applications

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Semiconductor Design Standard for Flip Chip Applications
This standard addresses semiconductor flip chip design requirements. Provides information for using standard semiconductor substrates, materials, assembly and test methods with established fabrication, bumping, test and handling practices. Electrical, thermal and mechanical chip design parameters and methodologies are covered in the standard, as well as the reliability aspects associated with these conditions and processes. The information applies to all new designs as well as modifications of non-flip chip designs. Developed by IPC and EIA.

SDO IPC: Institute for Interconnecting and Packaging Electronic Circuits
Document Number J026
Publication Date Not Available
Language en - English
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Revision Level 0
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Not Available IPC/EIA-J-STD-026 Revision