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IPC EIA/IPC/JEDEC-J-STD-075A

Current Revision

Classification of Passive and Solid State Devices for Assembly Processes

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Classification of Passive and Solid State Devices for Assembly Processes
EIA/IPC/JEDEC J-STD-075 picks up where J-STD-020 left off by providing test methods to classify worst-case thermal process limitations for electronic components. Classification is referenced to common industry wave and reflow solder profiles including lead-free processing. The classifications represent maximum process sensitivity levels and do not establish rework conditions or recommended processes for an assembler. IPC JEDEC J-STD-075A outlines a process to classify and label non-semiconductor electronic component’s Process Sensitivity Level (PSL) and Moisture Sensitivity Level (MSL) consistent with the semiconductor industry’s classification levels (J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Devices and J-STD-033, Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices). Developed by ECIA, IPC and JEDEC.

SDO IPC: Institute for Interconnecting and Packaging Electronic Circuits
Document Number J075
Publication Date Not Available
Language en - English
Page Count
Revision Level A
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Publish Date Document Id Type View
Not Available EIA/IPC/JEDEC-J-STD-075A Revision
Not Available ECA/IPC/JEDEC-J-STD-075 Revision
Not Available ECA/IPC/JEDEC-J-STD-075 Revision
Not Available ECA/IPC/JEDEC-J-STD-075 Revision
Not Available ECA/IPC/JEDEC-J-STD-075 Revision