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IEEE/IEC 62142-2005

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IEC/IEEE International Standard - Verilog(R) Register Transfer Level Synthesis

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- Inactive-Withdrawn. Replaces IEEE Std 1364.1-2002. To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364.

SDO IEEE: Institute of Electrical and Electronics Engineers
Document Number 62142
Publication Date Dec. 18, 2005
Language en - English
Page Count 116
Revision Level
Supercedes
Committee Design Automation
Publish Date Document Id Type View
Dec. 18, 2005 62142-2005 Revision