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IEEE/IEC 61523-4-2015

Historical Revision

IEEE/IEC International Standard - Design and Verification of Low-Power Integrated Circuits

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Adoption Standard - Active. A method is provided for specifying power intent for an electronic design, for use in verification of the structure and behavior of the design in the context of a given power management architecture, and for driving implementation of that power management architecture. The method supports incremental refinement of power intent specifications required for IP-based design flows.
This standard establishes a format used to define the low-power design intent for electronic systems and electronic intellectual property (IP). The format provides the ability to specify the supply network, switches, isolation, retention, and other aspects relevant to power management of an electronic system. The standard defines the relationship between the low-power design specification and the logic design specification captured via other formats [e.g., standard hardware description languages (HDLs)].
The purpose of this standard is to provide portable low-power design specifications that can be used with a variety of commercial products throughout an electronic system design, analysis, verification, and implementation flow.

SDO IEEE: Institute of Electrical and Electronics Engineers
Document Number 61523-4
Publication Date March 24, 2015
Language en - English
Page Count 351
Revision Level
Supercedes
Committee Design Automation
Publish Date Document Id Type View
Oct. 18, 2023 61523-4-2023 Revision
March 24, 2015 61523-4-2015 Revision