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IEEE/IEC 61523-4-2023

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IEEE/IEC International Standard - Design and Verification of Low-Power Integrated Circuits

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Adoption Standard - Active. A method is provided for specifying power intent for an electronic design, for use in verification of the structure and behavior of the design in the context of a given power-management architecture, and for driving implementation of that power-management architecture. The method supports incremental refinement of power intent specifications required for IP-based design flows.
This standard defines the syntax and semantics of a format used to express power intent in energy-aware electronic system design. Power intent includes the concepts and information required for specification and validation, implementation and verification, and modeling and analysis of power-managed electronic systems. This standard also defines the relationship between the power intent captured in this format and design intent captured via other formats (e.g., standard hardware description languages and cell libraries).
The standard enables portability of power intent across a variety of commercial products throughout an electronic system design, analysis, verification, and implementation flow.

SDO IEEE: Institute of Electrical and Electronics Engineers
Document Number 61523-4
Publication Date Oct. 18, 2023
Language en - English
Page Count 554
Revision Level
Supercedes
Committee Design Automation
Publish Date Document Id Type View
Oct. 18, 2023 61523-4-2023 Revision
March 24, 2015 61523-4-2015 Revision