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New IEEE Standard - Superseded.
This document provides a level of specification sufficient to design modules that are functionally, operationally, electrically, and mechanically compatible. Additional documents are necessary only to promote a higher degree of system level compatibility in manufacturers' products.
This IEEE standard specifies the functional, electrical, and mechanical requirements for a set of signal lines that constitute a backplane bus, and for the interfacing of boards connected to that bus. The bus provides the means for the transfer of binary digital information between boards over a single backplane. The number of physical modules is restricted to 24 due to electrical and mechanical constraints, even though slot addressing allows up to 31 modules. The modules may contain any combination of one or more processors and immediate peripherals such as memory, peripheral, and communication controllers. Figure 1 shows a block diagram of a typical board. %o connector pins are allocated for a serial bus, but the provision of such a bus is optional. The purpose of providing a serial bus would be to increase the degree of fault tolerance and survivability of the system. In any high integrity system an alternate control path is required in order to prevent major system faults and allow, at least partially, orderly operation in the event of a component failure associated with the parallel bus. A serial bus is the most cost-effective way of providing such an alternate control path. The definition of the serial bus is outside the scope of this standard. It is anticipated that a common serial bus protocol will be developed within the IEEE P1394 Working Group that will be applicable to all future parallel bus standards. Protocols are specified for the allocation of bus time to modules needing to conduct transactions with other modules over the bus. However, the standard does not lay down mandatory priority rules for modules to use when competing for use of the bus. These are considered the responsibility and privilege of the system implementer. The standard includes a full set of signaling rules to be followed by all modules in the distributed control acquisition process leading to bus mastership (Section 6). The standard also gives a full set of signaling rules for all modules participating in a bus transaction (Section 7).
| SDO | IEEE: Institute of Electrical and Electronics Engineers |
| Document Number | 896.1 |
| Publication Date | July 28, 1988 |
| Language | en - English |
| Page Count | 64 |
| Revision Level | |
| Supercedes | |
| Committee | Microprocessor Standards Committee |
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