Logo

IEEE 896.1-1991

Current Revision

IEEE Standard for Futurebus+(R) -- Logical Protocol Specification

$151.00


Sub Total (1 Item(s))

$ 0.00

Estimated Shipping

$ 0.00

Total (Pre-Tax)

$ 0.00


Stay effortlessly up-to-date with the latest standard revisions. When new versions are released, they're automatically charged and delivered to you, ensuring seamless compliance.

Document Preview Not Available...

Revision Standard - Inactive-Withdrawn. IEEE Std 896.1-1991 provides a set of tools with which to implement a Futurebus+architecture with performance and cost scalability over time, for multiple generations of single- and multiple-bus multiprocessor systems. Although this specification is principally intended for 64-bit address and data operation, a fully compatible 32-bit subset is provided, along with compatible extensions to support 128- and 256-bit data highways. Allocation of bus bandwidth to competing modules is provided by either a fast centralized arbiter, or a fully distributed, one or two pass, parallel contention arbiter. Bus allocation rules are provided to suit the needs of both real-time (priority based) and fairness (equal opportunity access based) configurations. Transmission of data over the multiplexed address/data highway is governed by one of two intercompatible transmission methods: (1) a technology-independent, compelled-protocol, supporting broadcast, broadcall, and transfer intervention (the minimum requirement for all Futurebus+systems), and (2) a configurable transfer-rate, source-synchronized protocol supporting only block transfers and source-synchronized broadcast for systems requiring the highest possible performance.

SDO IEEE: Institute of Electrical and Electronics Engineers
Document Number 896.1
Publication Date March 10, 1992
Language en - English
Page Count 208
Revision Level
Supercedes
Committee Microprocessor Standards Committee
Publish Date Document Id Type View
March 10, 1992 896.1-1991 Revision
July 28, 1988 896.1-1987 Revision