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IEEE 1364-1995

Historical Revision

IEEE Standard for Verilog Hardware Description Language

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New IEEE Standard - Superseded. The Verilog Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.
The intent of this standard is to serve as a complete specification of the Verilog Hardware Description Language (HDL). This document contains: -- The formal syntax and semantics of all Verilog HDL construct; s -- Simulation system tasks and functions, such as text output display commands; -- Compiler directives, such as text substitution macros and simulation time scaling; -- The Programming Language Interface (PLI) binding mechanism; -- The formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines; -- Informative usage examples; -- Listings of header Þles for PLI

SDO IEEE: Institute of Electrical and Electronics Engineers
Document Number 1364
Publication Date Oct. 14, 1996
Language en - English
Page Count 688
Revision Level
Supercedes
Committee Design Automation
Publish Date Document Id Type View
April 7, 2006 1364-2005 Revision
Sept. 28, 2001 1364-2001 Revision
Oct. 14, 1996 1364-1995 Revision