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IEEE 1076.4-2000

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IEEE Standard VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification

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Revision Standard - Inactive-Withdrawn. The VITAL (VHDL Initiative Towards ASIC Libraries)ASIC Modeling Specification is defined in this standard.This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit)components in VHDL.
To provide a standard method of modeling ASICs in VHDL. This method is aimed at providing efficient, accurate, and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs.
Current industry methods for designing complex chip-level designs rely on proprietary solutions which are based on specific commercial tools. This standard provides an effective means of performing those designs in a standard, non-proprietary manner that is independent of specific tools. This promotes cost effective design flows and promotes healthy levels of competition in the electronic design industry. This standard builds on the work of IEEE 1076 VHDL which is a standard hardware description language designed to allow such tool independent electronic design.

SDO IEEE: Institute of Electrical and Electronics Engineers
Document Number 1076.4
Publication Date Sept. 28, 2001
Language en - English
Page Count 448
Revision Level
Supercedes
Committee Design Automation
Publish Date Document Id Type View
Sept. 28, 2001 1076.4-2000 Revision
May 17, 1996 1076.4-1995 Revision