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IEEE 1005-1991

Historical Revision

IEEE Standard Definitions and Characterization of Floating Gate Semiconductor Arrays

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New IEEE Standard - Superseded. An introduction to the physics unique to this type of memory and an overview of typical array architectures are presented. The variations on the basic floating gate nonvolatile cell structure that have been used in commercially available devices are described. The various reliability considerations involved in these devices are explored. Retention and endurance failures and the interaction between endurance, retention, and standard semiconductor failure mechanisms in determining the device failure rate are covered. How to specify and perform engineering verification of retention of data stored in the arrays is described. Effects that limit the endurance of the arrays are discussed. The specification and engineering verification of endurance are described. The more common features incorporated into the arrays and methods for testing these complex products efficiently are addressed. The effects that various forms of ionizing radiation may have on floating gate arrays and approaches to test for these effects are covered. The use of floating gate cells in nonmemory applications is briefly considered.
This standard describes the underlying physics and the operation of floating gate memory arrays, specifically, UV erasable EPROM, byte rewritable E2PROMs, and block rewritable "flash" EEPROMs. In addition, reliability hazards are covered with focus on retention, endurance, and disturb. There are also clauses on the issues of testing floating gate arrays and their hardness to ionizing radiation.

SDO IEEE: Institute of Electrical and Electronics Engineers
Document Number 1005
Publication Date Oct. 17, 1991
Language en - English
Page Count 41
Revision Level
Supercedes
Committee
Publish Date Document Id Type View
Feb. 9, 1999 1005-1998 Revision
Oct. 17, 1991 1005-1991 Revision